MOS battery backup controller for microcomputer random access memory

ABSTRACT

MOS Control circuitry for incorporation on a microcomputer IC chip for assuring adequate power to maintain the data in an associated static random access memory. A rechargeable battery provides standby power, and the voltage level of the battery is compared with the microcomputer V cc  supply. Whenever V cc  drops below a predetermined level, such as the standby battery voltage level, the circuitry disconnects the V cc  from the memory input power and replaces it with standby battery power. When V cc  is returned to the system, a gate applies a trickle charge to the battery.

TECHNICAL FIELD

This invention relates to metal oxide semiconductor (MOS) circuitry andparticularly to on-chip MOS circuitry for switching to standby batterypower upon loss or reduction of a microcomputer system supply voltage.

BACKGROUND ART

Basic present day microcomputers generally include a microprocessor withinput-output ports, a read-only memory (ROM) containing permanentmicroprocessor operating instructions or programs, and a static randomaccess memory (RAM) for temporary storage of data. All components areusually formed on one integrated circuit chip and operate from onecommon power source.

Most modern random access memories are fabricated with N-channel silicongate MOS transistors. They are designed for static operation without theneed for complex refreshing circuitry, and therefore require acontinuous constant voltage source to maintain the states of the memorylatches. The data stored in a static RAM will be lost if power isremoved or if the applied voltage is even temporarily reduced to thepoint where the internal memory latches cannot hold their states.

The circuitry of the present invention prevents the loss of memoryysustaining power if the regular system power supply fails or falters.

DISCLOSURE OF THE INVENTION

Briefly described, the invention comprises circuitry including anon-chip MOS supply voltage comparator coupled to the system V_(cc)supply conductor and also to an external standby rechargeable battery.The comparator generates a high output whenever the V_(cc) level fallsbelow that of the battery. The comparator output controls the operationof a MOS battery backup controller which includes gates that connect thebattery to the RAM voltage conductor while opening switches thatdisconnect the V_(cc) conductor.

BRIEF DESCRIPTION OF THE DRAWING

The single drawing is a schematic diagram illustrating the backupcontroller of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

As illustrated in the drawing, V_(cc) power enters the circuitry onconductor 10 and standby power, V_(b), preferably supplied by arechargeable battery 12, enters the circuitry on conductor 14. Thestandby control circuitry normally applies V_(cc) power to the outputconductor 16 which may supply a random access memory. However, if theV_(cc) source fails or the voltage level on the conductor 10 drops belowa predetermined level, which may be the voltage level of the battery 12,the control circuitry disconnects the V_(cc) from the output conductor16 and replaces it with standby power from the battery 12.

The control circuitry includes a MOS supply voltage comparatorcomprising the eight transistors 18 through 25. it will be noted thattransistors 18, 20 and 24 are heavy depletion transistors having theusual relatively high negative threshold and in the circuitryillustrated they are always on. Depletion transistor 18 and theenhancement transistor 19 are coupled in series to form a voltagedivider. Transistor 18 is coupled to conductor 16 which, as indicatedabove, is normally at a V_(cc) level. Transistor 19 is coupled to aground reference, and the gates of both transistors are coupled togetherand to their point of source-to-drain interconnection. Transistors 20and 21 are connected as a conventional MOS inverter circuit. The drainof transistor 20 is coupled to the V_(b) conductor 14 and the source oftransistor 21 is coupled to ground reference. The gate of transistor 20is coupled to the interconnection of transistors 20 and 21 and the gateof transistor 21 is coupled to the output point at the interconnectionof the voltage divider pair 18 and 19.

Transistors 18, 19, 20, and 21 form a current mirror. For a given levelof V_(cc) voltage on conductor 16, the voltage divider pair comprisingtransistors 18 and 19 establish a reference current which is mirroredinto the inverter at the gate of transistor 21. If the V_(cc) level onconductor 16 is sufficiently high to provide the required current, thenthe voltage at the inverter output point 28 is lower than the divideroutput voltage at interconnecting point 26. If, on the other hand, theV_(b) level on conductor 14 is higher than the V_(cc) level on conductor16, then the voltage at point 28 is greater than that at point 26.

The output point 28 of the inverter including transistors 20 and 21 isapplied to a buffer circuit comprising transistors 22 and 23 in series.The drain of transistor 22 is connected to the V_(b) conductor 14 andthe source of transistor 23 is connected to ground reference. The gateof transistor 22 is connected to the conductor 16 and the gate oftransistor 23 is connected to the output point 28 of the inverter. Thus,if the output 28 is at a high level, transistor 23 is conductive and itsoutput point 30 at the connection of transistors 22 and 23 is low. Asignal output may be taken at this point 30; however, in the circuitrydescribed herein, the positive high output is desired whenever theV_(cc) level on conductor 10 drops below a predetermined level.Therefore, the output signal at point 30 of the buffer is inverted by asecond inverter comprising transistors 24 and 25 in series. Thisinverter output taken from the interconnecting point 32 provides therequired signals from the gating circuit to be described.

The switchover point between the V_(cc) and V_(b) will normally occurwhen V_(cc) is equal to V_(b) and the voltage at inverter output 28equals the voltage at the divider output 26. This switch point willoccur if the enhancement transistors 19 and 21 are identical. Ifdesired, the switch point may be altered by appropriately changing thephysical sizes of the MOS transistors in the circuitry so that thesupply switchover points may occur at different levels of V_(cc) .

As previously mentioned, V_(cc) power from conductor 10 is normallyapplied, during operation, to the output conductor 16 through aswitching transistor 34, the gate of which is connected to the output ofa conventional charge pump comprising transistors 36, 38 and 40 inseries. Both the gate and the drain elements of transistor 36 areconnected to the V_(cc) conductor 10 and the gates of the transistors 38and 40 are connected to their drain elements. The gates of transistors38 and 40 are also coupled through capacitors to a two-phasemicrocomputer clock which operates to pump the charge pump output to alevel that is more positive than the V_(cc) level. This higher voltageis filtered by a suitable capacitor 42 and applied to the gate of thetransistor 34 to turn on this transistor to provide conduction betweenthe V_(cc) conductor 10 and the output conductor 16. It will be notedthat any failure in the microcomputer clock circuitry, as well as theV_(cc) level, will result in a drop of the gate voltage on thetransistor 34 with the consequent disconnecting of the V_(cc) from theoutput conductor 16.

When V_(cc) power to the microcomputer is turned off, the level ofV_(cc) on the conductor 10 will decay and the two-phase clock input tothe charge pump will be removed. The signal which is indicating that themicrocomputer power is on or off is applied to the gate of a transistor44 that is coupled to ground reference and is in series with a heavydepletion load transistor 46 coupled to the output conductor 16. Thegate of the heavy depletion transistor 46 is coupled to theinterconnection between transistors 44 and 46 and the transistor 46 isalways on. A high "on" signal applied to the gate of transistor 44renders that transistor conductive and results in a low input signal onthe gate of transistor 48, which is connected between ground referenceand the output of the charge pump. When microcomputer power is turnedoff, a low signal is applied to the gate of the transistor 44 to renderit non-conductive so that the gate of transistor 48 goes to its highlevel to render transistor 48 conductive. Therefore, even before theV_(cc) level has begun to decay as a result of power turnoff, the chargepump output conductor is grounded to discharge the capacitor 42 and toturn off the main switching transistor 34 between the V_(cc) conductor10 and the output conductor 16.

The V_(b) conductor 14 is coupled to the circuitry output conductor 16through a heavy depletion transistor 50, the gate of which is connectedto the output point 32 of the voltage comparator circuitry. Thus, whenthe voltage comparator generates a high output resulting from thelowering of the V_(cc) level, transistor 50 is fully turned on toprovide a current path between the external battery 12 and the circuitryoutput conductor 16. The output conductor 16 is therefore maintained ata proper voltage, either by the V_(cc) power or by the V_(b) power sothat the random access memory being supplied with the output voltage onconductor 16 will retain the data contained therein.

Upon return of V_(cc) to its normal level, the output on the charge pumpwill again render the switching transistor 34 conductive and the outputof the comparator will remove the standby power from the outputconductor. The output of the charge pump is also connected to the gateof a transistor 52 which is connected between the V_(cc) conductor 10and the V_(b) conductor 14. When transistor 52 is turned on by theoperation of the charge pump, current from conductor 10 is appliedthrough the conductor 14 and into the external rechargeable standbybattery 12 to thereby maintain the charge on the battery in readinessfor future use.

We claim: .[.1. In a MOS microcomputer circuit, a voltage comparatorcoupled to a V_(cc) conductor and to a source of standby power forgenerating an output signal when the V_(cc) level drops below apredetermined voltage level of said standby power, said comparatorcomprising: transistors..].
 4. MOS microcomputer system computer controlcircuitry for maintaining memory sustaining voltage to a static randomaccess memory upon failure of the system to maintain a V_(cc) level,said control circuitry comprising:(a) input means for connecting anexternal battery to said control circuitry; (b) a MOS voltage comparatorcoupled to said input means and to a V_(cc) conductor, said comparatorgenerating an output signal when the V_(cc) level drops by apredetermined amount wherein said voltage comparator comprising: (i) avoltage divider including first and second MOS transistor coupled inseries between the V_(cc) conductor and ground reference, the gates ofsaid first and second transistors being coupled together and to theinterconnection of said first and second transistors; (ii) an invertercircuit including third and fourth MOS transistors coupled in series,said third transistor being coupled to said input means and said fourthtransistor being coupled to ground reference, the gate of said thirdtransistor being coupled to the interconnection of said third and fourthtransistors and the gate of said fourth transistor being coupled to theinterconnection of said first and second transistors; (iii) a buffercircuit including fifth and sixth series MOS transistor, said fifthtransistor being coupled to said input means and said sixth transistorbeing coupled to ground reference, the gate of said fifth transistorbeing coupled to V_(cc) and the gate of said sixth transistor beingcoupled to the interconnection of said third and fourth transistors, theoutput of said buffer circuit being at the interconnection of said fifthand sixth series transistors; and (iv) a second inverter circuitincluding seventh and eighth series MOS transistors, said seventhtransistor coupled to said input means and said eighth transistorcoupled to said ground reference, the gate of said eighth transistorbeing coupled to the interconnection of said sixth and seventhtransistors, the interconnection between said seventh and eighthtransistors providing the output of said second inverter circuit to saidMOS gating circuitry; and (c) MOS gating circuitry coupled to said inputmeans, to said v_(cc) conductor, and to the output conductor andresponsive to the output signal of said comparator for coupling saidV_(cc) conductor to said output conductor when the voltage level on saidV_(cc) conductor remains at least as high as the voltage level of saidinput means, and for disconnecting the coupling to said V_(cc) conductorand coupling said input means to said output conductor upon a loweringof said V_(cc) by a predetermined amount.
 5. The control circuitryclaimed in claim 4 wherein said gating circuitry includes a MOS chargepump coupled to said V_(cc) conductor and to a two-phase clock source,said charge pump generating an output voltage more positive than saidV_(cc) level for turning on MOS gates coupled between said V_(cc)conductor and said output conductor. The control circuitry claimed inclaim 5 wherein said MOS gating circuitry provides a battery chargingcurrent from said V_(cc) to said input means.
 7. The control circuitryclaimed in claim 6 further including switch means responsive to a signalindicative of the existence of input power, said switch means coupledbetween the output of said charge pump and ground reference forgrounding said output upon the removal of said input power.